This invention relates to a technique applied to semiconductor integrated circuits, and which is particularly effective when applied to a bipolar type of semiconductor integrated circuit. The technique of the invention can be applied effectively to, for example, a PLA (Programmable Logic Array) consisting of a NAND (or AND) gate array and a NOR (or OR) gate array.
The inventors of the present invention have clarified that the following problems are encountered when fabricating logic circuits by semiconductor integrated circuit techniques such as PLA circuit techniques.
An outline of a PLA as a logic circuit will first be given briefly. A PLA consists of a NAND or AND gate array and a NOR or OR gate array. The NAND or AND gate array first executes a NAND or AND operation for a plurality of logic inputs applied thereto from outside. Next, the NOR or OR gate array executes a NOR or OR operation for a plurality of logical output signals produced from the NAND or AND gate array. A logical output satisfying predetermined logic conditions is thus obtained from the NOR or OR gate array. In this case, the logic conditions can be set as required in advance by the wiring of the internal circuits of each of the NAND or AND and NOR or OR gate arrays. In other words, the logic conditions can be programmed.
A NAND or AND gate array usually consists of a large number of logic elements arranged in a regular order, and a wiring network provided between the electrodes of these logic elements.
In a PLA of this kind, an extremely large number of logical elements are used, particularly in the NAND or AND gate array, and the number of the lements increases rapidly with increasing circuit size. If a PLA is assembled using a bipolar semiconductor integrated circuit, therefore, an extremely large number of bipolar elements must be formed as the logic elements.
In this case, the number of elements can be reduced if IIL (Integrated Injection Logic) devices with a multi-electrode structure are used as the logic elements. However, since the structure of an IIL device is opposite to that of an ordinary bipolar transistor, it must be operated with a current gain in the reverse direction, that is, with an inverse current gain .beta..sub.i. This inverse current gain .beta..sub.i is much lower than the forward current gain .beta. of an ordinary bipolar transistor, so that the driving effect thereof, the so-called "drivability", is extremely low. This results in the problem that the number of electrodes that can be formed for one IIL device is limited. For this reason, an extremely large number of elements are still necessary when assembling a large-scale logic circuit using ILL devices. In order to actuate an IIL device, a constant current called an "injection current" must always flow, and this results in an increase in the current consumption. Since a large number of elements are used, this current consumption is even greater, the layout structure is more complicated, and a larger area is required. These are problems in the prior art that have been discovered by the inventors of the present invention.
"Electronics", p.p. 86-89, published on July 10, 1975 proposes a Schottky-IIL technique which reduces logic swings and improves the operating speed by the use of a large number of Schottky diodes for the output of an IIL device. Schottky diodes are formed by bringing a large number of electrodes into contact with the surface of an n.sup.- -type epitaxial layer. This article in "Electronics" also proposes an IIL-like complementary constant-current logic circuit in which a large number of Schottky diodes are used for the output of the circuit, and pnp current-source transistors and complementary npn switching transistors are formed within the same small isolation region.
The present invention is directed to eliminating the problems relating to the application of IIL devices to the PLA described above, and further develop the Schottky circuit technique described above.